`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/11/16 16:57:29
// Design Name: 
// Module Name: clkdiv_1M
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module clkdiv_1M(
    input clk,
    input rst,
    output reg clkdiv
    );
    parameter N=1000000;
    reg [31:0] cnt;
    initial cnt=32'b0;
    always @ (posedge clk or posedge rst)
    if (rst)
        cnt<=0;
    else if (cnt==N/2)
        cnt<=0;
    else
        cnt<=cnt+1;
    always @ (posedge clk or posedge rst)
    if (rst)
        clkdiv<=0;
    else if (cnt==N/2-1)
        clkdiv<=~clkdiv;
endmodule
